FA CMP technology for high dielectric constant gate dielectric/metal gate

The high dielectric constant gate dielectric and metal gate technology (hereinafter referred to as HKMG) allow Moore's Law to continue at the 45/32 nm node. The current HKMG process has two mainstream integration schemes, namely "first gate" and "back gate". The “gate” is also referred to as a replaceable gate (hereinafter referred to as RMG). When using this process, the high dielectric constant gate dielectric does not need to go through a high temperature step, so the VT offset is small and the reliability of the chip is higher. Therefore, the industry is more inclined to choose the RMG process when manufacturing high-performance chips. However, the RMG process involves more process steps and faces more process difficulties and design constraints. One of the difficulties is that flatness is extremely difficult to achieve.

The typical RMG process flow includes (Fig. 1): the formation of a temporary polysilicon gate structure, the deposition of a first interlayer dielectric (ILD0) silicon oxide, the ILD0 chemical mechanical polishing until the temporary polysilicon gate is completely exposed, and the etching removes the polysilicon gate. Polar, deposition of work function materials, deposition of metallic aluminum, and chemical mechanical polishing of metallic aluminum. As one of the RMG process steps, ILD0 chemical mechanical polishing is critical to the smooth formation of the HKMG structure.

Since the gate structure requires very strict dimensional control (WIW and WID), the lack of a process that strictly controls the final polishing thickness will lead to a series of process integration problems such as gate resistance fluctuation and insufficient gate filling. Source/drain exposure and more. These problems will ultimately damage the performance of the chip. In order to ensure the excellent performance and reliability of the chip, the manufacturing process must strictly control the thickness difference of WIW, WID and WTW.

Applied Materials has successfully developed a three-step CMP process on the Reflexion® LK machine to address WIW, WID and WTW thickness control issues during ILD0 chemical mechanical polishing. The first step (P1), grinding removes most of the ILD0 dielectric material; the second step (P2), continues grinding with FA, stops after contacting the silicon nitride layer in the gate region; the third step (P3), the gate The silicon nitride layer in the region is completely worn away and the polysilicon gate is completely exposed. Figure 2 demonstrates the entire process of silica grain removal in the trench region during ILD0 CMP.

Experimental details

Applied Materials' Reflexion® LK grinding machine includes a FA grinding disc and two standard rotary grinding discs, using a TItan ContourTM grinding head that controls the pressure in five separate zones (Figure 3). The FA grinding disc is equipped with a SlurryFreeTM fixed abrasive reel and a SlurryFree P6900 base polishing pad from 3M. The slurry grinding disc was equipped with an IC1010TM polishing pad manufactured by Dow Chemical Co., Ltd. and a polishing pad repairing brush manufactured by 3M Company. P1 uses a Semi-SperseR SS-12 silica slurry produced by Cabot Corporation; P2 uses a FA slurry; and P3 uses a dedicated slurry.

This article will unify the use of a simplified gate structure (Figure 4) to evaluate the performance of different processes. The structure of the gate region is from top to bottom: silicon oxide/silicon nitride/polysilicon/gate oxide/single crystal silicon, and “groove” refers to the region between the gate and the gate (structure: silicon oxide) / Monocrystalline silicon). In the measurement area having a size larger than 50 μm, the film thickness was measured using NanoTM 9010b from Nanometrics. For measurement points with a gate size of less than 100 nm, longitudinal section observation by scanning electron microscopy (SEM) is required. In this paper, a part of the sample is obtained by mechanical splitting to obtain the longitudinal section of the wafer; another part of the sample is partially cut by a focused ion beam (FIB) to expose the longitudinal section.

Results and discussion

P3 requires a non-selective slurry

Since the flatness requirement after P3 is very strict, the grinding of P3 tends to use a non-selective slurry. The slurry has a considerable abrasive rate on silicon nitride, silicon oxide and polysilicon. First, the grinding rate of silicon nitride must be high enough to ensure complete exposure of the polysilicon gate. If the polishing rate of silicon oxide is significantly lower than that of silicon nitride and polysilicon, it may cause the groove region to be significantly convex and deteriorate with over-grinding. If the polishing rate of polysilicon is significantly lower than that of silicon nitride and silicon oxide, the difference in height between the gate and the trench is very sensitive to insufficient or excessive grinding. The use of a non-selective slurry will reduce the variation in height difference between the gate and the trench due to the different P3 milling times.

P2 FA process can reduce WID thickness difference of trench silicon oxide after P3

The FA process has been widely used for direct grinding shallow trench isolation (STI). FA can selectively stop on the surface of silicon nitride and exhibit excellent polishing flatness and low concave defects. Similar to STI, the grinding of ILD0 also includes the step of stopping on the surface of the silicon nitride. This extremely low silicon nitride loss and very low silicon oxide recess defects make FA the key to WIW and WID thickness control in the ILD0 grinding process. In the gate-dense region, due to the small feature size, the concave defects are generally low regardless of the FA process or the highly selective slurry (HSS) grinding process (Fig. 5). However, in the peripheral region, the feature size may reach 50 microns or more, the HSS grinding process generally produces significant concave defects (>200?), while the FA grinding process still maintains low concave defects (<50?).

Therefore, the thickness difference of the trench silicon oxide WID after the FA process and the HSS process is compared, the former is significantly lower than the latter. Since P3 uses a non-selective slurry, the high-concave defects after P2 directly lead to a high difference in WID thickness of the trench silicon oxide after P3 (Fig. 5). The difference in WID thickness after P3 can be clearly seen from the SEM photograph of the longitudinal section of the wafer.

Biomass Clean Cook stove

Biomass Cook Stove,Wood Cook Stoves,Outside Camping Pellet Stove,Biomass Camping Stove

Xunda Science & Technology Group Co.ltd , https://www.xundatec.com