Design of Multi-channel Audio / Video Acquisition and Processing System Based on DSP
Currently, in digital image processing, due to the large amount of data and the difficulty of the algorithm, real-time performance has become one of the technical difficulties. If a special circuit is used, although the real-time performance is guaranteed, the flexibility of the system is greatly reduced. Therefore, it is urgent to seek a high-speed general-purpose digital signal processing system.
The TMS320DM642 (hereinafter referred to as DM642) type digital signal processor introduced by II Company can process 4 analog video and audio inputs, 1 analog / digital video and 1 analog audio signal output in real time, adapting to PAL / NTSC standard composite video CVBS or component Video Y / C format analog signal input, can be adapted to PAL / NTSC standard S terminal or digital RGB analog / digital signal output, can be adapted to standard microphone or stereo audio analog input and standard stereo audio analog output, with multi-channel acquisition data Real-time processing and analysis functions can realize data and image overlay display.
2 Introduction to DM642
DM642 digital signal processor can use 500 MHz or 600 MHz operating frequency, can complete up to 4.8 G operations per second, with online programming function, with a rich peripheral interface can be connected to a variety of memory, can be directly connected to the network , Is the preferred device for high-speed image processing.
The CPU of DM642 adopts the second-generation VelociTI.2 core structure, contains dual data paths, 8 arithmetic units, and can be executed every cycle
DM642 adopts a complete memory hierarchical architecture with 2-level memory. The Cache controller in 2-level memory can automatically complete the management and scheduling of the hierarchical memory architecture. External memory access and access to on-chip peripherals are accomplished through EDMA.
DM642 has 3 video input and output ports and multi-channel audio signal input and output serial ports. The external memory interface EMIF provides a 64-bit wide external bus data interface and supports glueless interfaces with various devices. DM642 also has a host parallel interface, peripheral device interconnection port, multi-channel cache serial port and general-purpose I / O port.
3 System function and hardware circuit design
3.1 Overall system structure
The overall structure of the system is shown in Figure 1. The image acquisition and pre-processing unit mainly completes the input of image signals, has multiplex signal multiplexing function, and digitizes and converts the format of the input analog video signal. The FPGA controls the logic of the system and the flow of image data, and can process the image data output by the DM642 and then output it to the image coding unit. The image processing unit uses DM642 for high-speed data processing and analysis. The image coding unit encodes the image data to form a standard analog video signal, which can be directly output to the display device.
For 4-channel video and 4-channel audio signals, the CPU can only process 1 channel of data at a time. The CEO address space of DM642 located outside the EMIF has expanded 2 SDRAMs of 4 Mx32 bit to store image acquisition data and image processing. Data to improve data collection and storage speed.
3.2 Video interface design
DM642 has 3 video ports, each of which can be configured as 2 channels up and down, but 2 channels must be video input port or output port at the same time. Combined with actual application, DM642 has 4 analog video inputs (cif format, resolution 352 × 288) and 1 analog video output.
The VPO A channel is configured as an 8-bit BT.656 video input or output port, connected to the first channel video input or video output. The VPl A channel is configured as an 8-bit BT.656 video input port, which is connected to the second channel video input. The VP2 A and B channels are configured as two 8-bit BT.656 video input ports, which are connected to the third and fourth channel video inputs. The B channel of VP0 and VPI is configured as MCASP, and then connects 4 audio Codec.
TVP5150 video encoder supports PAL / NTSC, CVBS or Y / C analog video input, 8-bit BT.656 digital video data stream output. SAA7105 video decoder supports 8-bit BT.656 digital video data stream input, PAL / NTSC CVBS or Y / C analog video output. The internal registers of the video encoder / decoder are programmed through the I2C bus of DM642 to realize different input and output. The corresponding pin functions of DM642 and TVP5150 are shown in Table 1.
The parameters of the video codec are configured through the I2C bus. Since the I2C slave address of the TVP5150 has only 2 options, it needs to be switched with the CBT3257 type 2 select l switch.
When used as a video input port, the line / field synchronization of the video data includes the EAV and SAV time base signal control in the BT.656 digital video data stream. The video port only requires a video sampling clock and a sampling enable signal (controls the sampling start) The TVP5150 uses the system clock SCLK to provide the sampling clock and the programmable pin GPCL to provide the sampling enable. As the video output port, the video port should provide the clock and line / field synchronization signals for SAA7105.
In the video output circuit, J1, J2, J3 can be configured as RGB output signals, J2, J3 can be connected to the S terminal, J1, J2, J3, J4, J5 can be directly output to the computer display. The specific interface circuit is shown in Figure 2 and Figure 3. The corresponding pin functions of DM642 and SAA7105 are listed in Table 2.
3.3 Interface design of multi-channel audio serial port
The author uses 4 analog audio inputs and 1 analog audio output, using TLV320AIC23B type audio codec / decoder, which supports microphone / stereo analog input / output and digital audio data stream output / input.
The PLL1708 programmable video / audio synchronous digital phase-locked loop provides a clock signal to McASP and TLV320AIC23B. The SCK02 port is connected to McASP's AHCLKX, and the SCK03 port is connected to TLV320AIC23B's main clock MCLK. The clock input of PLLl708 is 27 MHz. The corresponding pin functions of DM642 and TLV320AIC23B are shown in Table 3.
The AIC23B data port is configured as slave, and the 8 receiving / transmitting pins of McASP are configured as 4 receiving / 4 sending, respectively connected to the Dout / Din of 4 codecs. The receiving frame of McASP is synchronously configured as output, and simultaneously gives LRCout of 4 codecs. The transmission frame synchronization of McASP is configured as output, and it is also given to the LRCin of 4 codecs. McASP's transmit bit clock ACLKX is configured as an output (divided by AHCLKX), and BCLK for 4 codecs. The control port of the AIC23B is configured as I2C, which is switched by the CBT3257 type 2 select 1 switch. The specific circuit is shown in Figure 4.
In addition, pay attention to the power-on sequence of the CPU when powering the DM642: the CHU core should be powered on before I / O, and then powered off after I / O. The CPU core and I / 0 should be powered at the same time as much as possible. The time difference between the two cannot be Too large (<1 s), otherwise it will affect the life of the device or damage the device. The programmable clock circuit can solve the clock problem of the whole circuit well.
4 System software design
The system software includes system initialization settings, image processing algorithms, and screen overlay procedures. The specific software flow is shown in Figure 5.
4.1 System initialization setup program
Initialize the entire hardware system, including the power-on initialization of DM642, the setting of DM642 registers and system configuration pins, and the setting of registers for TVP5150 and SAA7105 using the I2C bus.
The boot mode of DM642 is to boot from EMIFA, set the pin AEA [22:21] to ll, and initialize the other configuration pins to default values. Peripheral configuration register (PERCFG) is used to configure the control video port, multi-channel buffer serial port, and multi-channel audio serial port, initialized to 0x0000 0079h. The device status register (DEVS-TAT) is used to control the status of each peripheral device of the circuit: EMAC, HPI, PCI, CPU clock frequency selection mode, circuit boot mode, EMIFA input clock selection, initialized to 0x0000 005Ch.
4.2 Image processing program
Processing and analyzing the collected image data and format conversion of the video stream, which can be composite video or component video, and can also be compressed and stored for later browsing.
4.3 Screen overlay
The data in the FPGA internal FIFO and the data output from the video port are mixed to complete the screen display function. There are several ways to superimpose the screen. The background is transparent, translucent, and opaque. The position of the superimposition can also be set arbitrarily. Just modify the coordinates of the starting point of the superimposed image and add the corresponding image information to the corresponding video image queue .
4.4 Video / audio signal acquisition and storage and image data reading program
For 4-channel video signals and 4-channel audio signals, the CPU can only process 1 channel of data at a time, so two 4Mx32bit SDRAMs are expanded outside the DM642 chip. At any time when the system is working, one is used for image acquisition The acquisition part writes image data to the storage area, and the other is used for external reading of the image data. The DSP can read the image data in the storage area. The important feature of the dual SDRAM structure is that the data operation of the storage area by the DSP is switched back and forth. When the A / D conversion data is written to SDRAM-1, the FPGA will send an interrupt signal to the DSP. At this time, while the DSP reads the data in SDRAM-1, the A / D conversion data is written to SDRAM-2. When SDRAM- When the data in 2 is full, the FPGA sends an interrupt signal to the DSP. At this time, the DSP reads the data in SDRAM-2, and at the same time, the A / D conversion data is written in SDRAM-1, so alternately, the data is written and read Take at the same time. Because the speed at which the DSP reads the data in the SDRAM is much faster than the speed at which the A / D conversion writes data, it allows simultaneous acquisition and external access, and the ping-pong switching using two storage area operations meets the real-time data exchange requirements.
Because the data operation of the DSP to the storage area is switched back and forth, it is necessary to use interrupts to achieve access. The specific implementation is to set an interrupt in the DSP, here select INT6 as the interrupt trigger pin. When the external interrupt signal arrives, the corresponding interrupt service routine executes the interrupt response.
5 Conclusion
The system can process 4 channels of digital video in CIF format at the same time, and can be dynamically switched. The total sampling rate can reach 100 frames / second, and the rate of each channel is 25 frames / second, which can fully guarantee real-time image acquisition.
There are various methods for superimposing images, and the position of the superimposition can also be arbitrarily set by modifying the coordinates of the starting point of the superimposed image. DM642 also has a network interface, which can compress the output video signal and transmit it in real time by the network.
The image acquisition and processing system based on DM642 can be widely used in set-top boxes, IP video phones, network video conferences and other fields.
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