SSI interface technology and its application in audio processing
TLV320DAC23 is a high-performance stereo high-end codec chip launched by TI. It supports multiple sampling rates and multiple audio formats, and has the characteristics of low power consumption and small package. It is widely used in portable digital audio processing systems.
1 Working principle of synchronous serial interface SSI
Synchronous SerialInterface (SSI) is a full-duplex serial interface that allows the chip to communicate with multiple serial devices. It is a more commonly used interface method in high-precision absolute value angle encoders. It adopts the active reading mode of the host, that is, under the control of the clock pulse issued by the master, synchronous transmission starts from the most significant bit (MSB) data. The SSI module structure is shown in Figure 1.
It can be seen from the figure that the SSI module is composed of a sending circuit, a receiving circuit, a serial clock, and a frame synchronization clock generating circuit. The transmission circuit and the reception circuit are independent of each other, but share the serial clock and the frame synchronization clock.
1. 1 SSI module pin signal description
SSLCLKIN: SSI clock input signal.
SSLBCLK: SSI serial bit clock.
SSLMCLK: SSI serial master clock signal, in SSI master mode,
This signal also serves as an oversampling clock signal.
SSI_FS: SSI serial frame synchronization signal.
SSLRXD: SSI serial receive data signal.
SSI_TXD: SSI serial transmission data signal.
1.2 The operation mode of SSI
SSI has three basic synchronous operation modes: normal mode, network mode and gate clock mode.
The normal mode is the simplest mode. Only one word can be transmitted in one frame, and each frame needs a frame synchronization signal to control synchronization; the network mode is mainly used in the case of multiple time slots, and two words can be transmitted in one frame to 32 words are not equal; in the gate clock SSI_BCLK mode, the serial bit clock SSI_BCLK indicates the valid data on the sending pin or receiving pin, so no frame synchronization signal is needed.
In addition to the above three basic modes, for audio applications, SSI also supports two derivative modes-I2S mode and AC97 mode, which are used to transmit I2S and AC97 audio format data, respectively.
1.3 Initialization of SSI
The correct sequence to initialize the SSI module:
â‘ Power on or restart SSI (SSI_CR [SSI_EN] = 0), that is, turn off the SSI module function.
â‘¡ Configure SSI module. The registers involved include the control register SSI_CR, the interrupt enable register SSI_IER, the transmit configuration register SSI_TCR, the receive configuration register SSI_RCR, and the clock control register SSI_CCR.
â‘¢ Set the necessary interrupt or DMA through the SSI_IER register.
â‘£Set SSI_CR [SSI_EN] = 1 to allow SSI module function.
⑤Set SSI_CR [TE / RE] to start sending / receiving data.
1.4 The working process of SSI
(1) Send data
In single channel, data is transferred from the serial transmit data register SSI_TX0 to the transmit shift register TXSR, and then sent out through the serial transmit pin SSI_TXD, and then determines whether to generate a transmit interrupt according to user settings. If the transmit buffer TXFIFOO is allowed, SSI_TX0 continues to fetch data from TXFIFOO until all data in TXFIFOO is sent, and then decides whether to generate a transmission interrupt according to user settings. When dual-channel, the transmit shift register TXSR takes data from SSI_TX0 and SSI_TXl alternately.
(2) Receive data
In single channel, the data comes in from the serial receiving pin SSI_RXD, and is transferred from the receiving shift register RXSR to the receiving data register SSI_RX0, and then determines whether to generate a receiving interrupt according to user settings. If the receive buffer RXFIFOO is allowed, SSI_RX0 writes data to RXFIFOO and continues to obtain data from the receive shift register. When dual channels, the receive shift register RXSR alternately transfers data to SSI_RX0 and SSI_RXl.
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