Full-chip verification of mixed-signal SoC using AMSVF
In these SoC circuits, due to the inclusion of data converters, power management and other analog circuits, mixed-signal design is inevitable and more and more. In mixed-signal SoC design, in order to avoid chip remanufacturing and ensure the success of one-time tape-out, full-chip mixed-signal verification becomes a key link. Traditionally, in complex mixed-signal SoC designs, different teams independently verified digital and analog components, and did not perform full-chip comprehensive verification. The main reason is that there was not enough powerful EDA tools to complete this important task. If all integration and interface problems are only solved in the test platform, it is difficult to ensure the correct connection and timing matching of the mixed signal. With the advent of high-speed SPICE simulation tools, designers can perform verification of the entire chip system at the transistor level, which is a more effective verification method. This method has high accuracy and can perform a comprehensive functional analysis. However, this type of verification can only be performed at the last stage of the design cycle, when all units and custom components have been designed. In addition, the simulation speed of this method is sometimes very slow, and a lot of hardware resources must be used. For complex systems including microprocessors, ROM, RAM, PLL, etc., because the number of components is too large, high-speed SPICE simulator is almost impossible to perform full-chip transistor-level simulation.
However, the verification methodology should be run through the entire design stage, not just the final verification stage. At the same time, in order to achieve a perfect balance between accuracy and speed for mixed-signal SoC verification, designers may want to maintain some important analog modules (such as ADC, PLL) as SPICE netlists, while the other parts are Verilog behavioral modules . At this time, designers can choose to use transistor-level circuits to replace specific behavior modules, and continue the design verification process in a timely and efficient manner.
In order to achieve accurate and fast full-chip verification, a new analog solution came into being.
AMS Designer and AMSVF
As a new generation of simulators, AMS Designer is based on the reliable technology of Virtuoso Spectre, Ultrasim Simulator and Incisive Unified Simulator engines, and is a single-core (Single Kernel) mixed-signal simulator. It provides two simulation solvers-Spectre and Ultrasim, and supports almost all languages ​​and SPICE netlist specifications. The Ultrasim solver has high performance, accuracy comparable to SPICE, and almost unlimited capacity, so it is more suitable for large-scale full-chip design.
Although AMS Designer provides a friendly graphical user interface for the DFII process, for mixed-signal verification, most designers require the application to perform full-chip verification in the command line mode. The reason is not only because the command line mode provides a powerful and convenient batch run function, but also because the design itself is based on a text document without a schematic, or without a GUI environment. For this application, AMSVF (AMS verification process) is more suitable.
Application mode of AMSVF
Inheriting NC-Verilog, the use of AMSVF supports ncverilog single-step mode, which is mainly for Verilog-XL users; and the 3-step mode will call ncvlog to analyze the input file, call ncelab to build the circuit structure, and then call the ncsim simulator to simulate the circuit.
At present, AMSVF can provide support for digital test platforms, and its application mode is shown in Figure 1.
Figure 1 AMSVF application mode
Verilog / VHDL top layer can also instantiate SPICE subckt. For VHDL test platform, Verilog wrapper is needed. In addition, the top layer can call other Verilog / VHDL modules. This application mode is named "Verilog on top". The middle-level SPICE subckt can also instantiate the lowest-level Verilog / VHDL module. This application mode is named "Sandwich" or "SPICE in middle". In addition, in some complex designs, AMSVF also supports multiple "Sandwich" application modes, such as "Verilog-SPICE-Verilog-SPICE-Verilog".
These two application modes are very convenient for users' full chip verification applications. For a pure digital system design, in order to obtain accurate results, users can replace some Verilog modules with SPICE netlists, and even use parasitic parameters to obtain more accurate simulation results. Because there are too many physical components, the simulation speed may become slower. At this time, users can use Verilog / VHDL behavior-level modules for basic gates in the SPICE netlist. Then, the "Sandwich" application model can be realized. This means that users can switch between application modes freely and simply. funcTIon ImgZoom (Id) // Re-set the picture size to prevent the form from being broken {var w = $ (Id) .width; var m = 650; if (w <m) {return;} else {var h = $ (Id) .height; $ (Id) .height = parseInt (h * m / w); $ (Id) .width = m;}} window.onload = funcTIon () {var Imgs = $ ("content"). getElementsByTagName ( "img"); var i = 0; for (; i
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