Two-to-four-wire converter connected to full-duplex bus
Multipoint data communication networks such as Profibus, Modbus, and BACnet typically rely on RS-485 dual-wire half-duplex or four-wire full-duplex bus systems. These systems can span hundreds of meters and are designed to handle significant ground potential differences (GPD). However, these voltage fluctuations can exceed the common-mode range of transceivers, potentially causing damage to connected devices. To prevent this, an electrically isolated transceiver is used to separate the control electronics of the bus node from the actual transceiver stage on the bus.
Figure 1: A block diagram showing a hybrid network using a 2-4 line converter.
To ensure the converter operates independently of the data rate, the driver and receiver of the converter are controlled based on the logic state of the bus. At every bit interval, the bus driver is active, allowing the converter to function without being dependent on the signal's data rate.
The control logic is straightforward. Drivers D1 and D2 are only enabled when the opposite receiver (R1 or R2) outputs a low signal. During idle periods, both receivers output high due to the fault protection voltage VFS (> 200 mV), which is then inverted by a gate to activate the receiver while turning off the driver.
In the half-duplex to full-duplex direction (as shown in Figure 2, left to right), a negative bus voltage at R1 triggers D2, which drives the bus with a negative output. Once the bus voltage becomes positive, D2 turns off, but its output remains high due to the fault protection resistor RFS.
(Note: Throughout this process, R2’s output remains high, ensuring that R1 stays active while D1 remains inactive.)
Figure 2: Timing diagram for the half-duplex to full-duplex conversion.
In the reverse direction—full-duplex to half-duplex (Figure 3, right to left)—a negative voltage at R2 activates D1, which drives the two-wire bus with a negative voltage. When the bus voltage becomes positive, D1 turns off after a delay. During this time, it continues to drive the bus with a negative voltage before switching to high impedance, preventing any transient issues at the R1 output.
We recommend that the minimum delay time be set to 1.3 times the maximum propagation delay of the driver, accounting for component tolerances, inverter thresholds, and supply voltage variations. The required RD value can be calculated using Equation 1, given the capacitance:
Equation 1
Where tPLH-max is the maximum low-to-high propagation delay of driver D2, VIT+min is the minimum positive input threshold of the Schmitt-triggered inverter, and VCC-max is the maximum supply voltage.
After D1 turns off, the bus voltage VFS, created by the fault protection resistor RFS, remains high. When the bus voltage at R2 returns to negative, the CD capacitor discharges quickly through the discharge diode DD, activating the circuit again. The timing diagram in Figure 3 illustrates how a remote receiver on the half-duplex bus converts the negative voltage into a low bit, while a high bit consists of a positive voltage and residual VFS.
Figure 3: Timing diagram for the full-duplex to half-duplex conversion.
Both converter ports require isolated power supplies VISO-1 and VISO-2 derived from a central 3.3V source. Figure 5 shows the schematic for this design. To avoid peak voltage issues under no-load conditions, each rectified output includes a minimum load resistor of 2 kΩ.
Figure 5: Isolated power supply design for VISO-1 and VISO-2.
In summary, a two-to-four-wire converter enables the connection of a single half-duplex transceiver or an entire half-duplex bus to a full-duplex system. When connecting this converter to a full-duplex bus, it's important to note that the master node's microcontroller must switch from full-duplex to half-duplex transmission mode when communicating with the converter node.
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